System-On-Chip Test Architectures: Nanometer Design for Testability

System-On-Chip Test Architectures

Nanometer Design for Testability

2007 • 893 pages
System-On-Chip Test Architectures: Nanometer Design for Testability

System-On-Chip Test Architectures: Nanometer Design for Testability

Publisher: Morgan Kaufmann

Type: Physical Book

Language: English

Pages: 893

Release Date: 2007-11-01

ISBN 10: 0080556809

ISBN 13: 9780080556802

Readers: 1

Country: United States of America

Data Score: 1790